Many conventional electrically programmable read only memory (EPROM) cell arrays are of the virtual-ground design. Adjacent columns of the memory cells share a bit line such that first ends of the current paths of an adjacent pair of cells on any one row are connected to one bit line. The other ends of the current paths of the cells are connected to different array source or decoded ground lines.
In order to read a cell, an array source or decoded ground on one end of a current path of a selected memory cell is brought low. The bit line is connected to a voltage bias source. Since the current path of the memory cell is interposed between the bit line and the selected array source, its conductance state may be ascertained by sensing the voltage level of the bit line. If the voltage level on the bit line falls, it is a sign that the state of the selected cell is conductive, and a logic "1" is read out. If the voltage level on the bit line remains high, the selected memory cell is sensed as nonconductive and a "0" is read out.
As will be described in more detail below, a cell is rendered conductive or not by the selective placement of charge on its floating gate. The more charge appears on a floating gate, the less conductive the cell is made. As more charge becomes resident on the floating gate, a higher and higher read voltage on the control gate of the cell needs to be applied in order to render the current path of the selected cell conductive. A cell may be tested to determine if sufficient charge has been placed on its floating gate by applying a predetermined test voltage, equivalent to voltage supply level plus a guard band, to the control gate and then reading the cell.
In order to increase reading speed, the virtual or decoded ground for every nonselected cell is connected to a voltage bias source. Because of this, a significant contribution of the current passing through the current path of the selected cell also passes through the current path of an adjacent yet-to-be programmed cell from an array source, which is in turn connected to the voltage bias source. As will be explained in more detail below, this current contribution will often times cause the misreading of the selected cell as being in a nonconductive or "0" state. Programming the adjacent cell from which the current contribution came will then cause the selected cell to be read as the "1" in normal operation, causing an error.
For the foregoing reasons, a need has arisen to develop methods and apparatus for correctly ascertaining the state of a memory cell during a program verify mode of the array.